Future electronic systems like autonomous systems using high-performance computing (HPC) and edge computing systems, sensor-integrated systems and bio-integrated devices will require more and more functions that cannot be managed by a single chip, even if advanced system on chip (SoC) concepts are used. In addition, a paradigm shift is taking place in many applications, in that data is progressively processed at a more localized level – from the cloud to the edge and down to the sensor node, thereby enabling meaningful information to be extracted, transmitted, stored or acted upon faster. 3D-stacking is also needed to realize smart sensor systems that aggregate a large amount of data and therefore have to be placed in close vicinity to the data processing, the data storage components and the transmission elements. Also, the increasingly higher costs for further node miniaturization in the IC manufacturing process will also promote the interconnection of chiplets. This means that intellectual property (IP) blocks made in different technology nodes will be combined on an interposer to reduce cost by increasing the production yield (smaller chips) and reuse across applications. In addition to the aforementioned approaches, optical intra-chip and intra-board communication need to be created in order to dramatically speed up communication and to significantly lower energy consumption
Therefore heterogeneous integration will appear at the chip package and organic substrate or panel level which will be discussed in this PDC.
- Introduction to new IC trends
- Implications for Wafer Level Packaging
- Implications for Panel Level Packaging
R&D Engineers and Decision Makers of the Semiconductor Industry for Advanced Packages